ISL35822LPIK【PDF 4/75 页】IC CLOCK/DATA RECOVERY 192EBGA-B

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8b/10b Coding and Decoding

8 Bit Mode

If 8B/10B encoding/decoding is turned on, the ISL35822

expects to receive a properly encoded serial bit stream. The

serial bit stream must be ordered “abcdeifghj” with “a” being

the first bit received and “j” the last. If the received data

contains an error, the Retimer will re-transmit it as an

ERROR or /E/ character. The character transmitted may be

controlled via the ERROR code Registers [3,4].C002’h,

Table 66 and Table 82. The internal decoding into, and

encoding from, the FIFOs is listed in Table 1 below. If the

TRANS_EN bit or XAUI_EN bit (MDIO Registers at

addresses [3,4].C001’h, see Table 64 and Table 81 are set,

all incoming XAUI or CX4/LX4 IDLE patterns will be

converted to the (internal) XGMII IDLE pattern set by the

respective PCS or PHY XS control registers at addresses

[3,4].C003’h, with a default value 107’h, the standard XGMII

IDLE code (see Table 67 and Table 83) in the internal FIFOs.

The first full column of IDLES after any column containing a

non-IDLE will be stored in the respective elasticity FIFO, and

all subsequent full IDLE columns will repeat this pattern, until

another column containing a non-idle is received. If in

addition either of the AKR_SM_EN or XAUI_EN bits in the

respective MDIO registers at Addresses [3,4].C001’h is set

(see Table 64 and Table 81, these IDLEs will be sequenced

on transmission into a pseudo-random pattern of ||A||, ||K||,

and ||R|| codes according to the IEEE 802.3ae specified

algorithm. If neither of the AKR_SM_EN and XAUI_EN bits

are set, the internal IDLEs will all be transmitted as /K/

codes. Elasticity will be achieved by adding or deleting

columns of internal IDLEs.

If neither the TRANS_EN bit nor the XAUI_EN bit is set (for

either the PCS or the PHY XS), the incoming XAUI IDLE

codes will all be decoded to the appropriate XGMII control

code values in the respective internal FIFO. If the AKR_EN

or XAUI_EN bits are set, they will be sequenced into a

pseudo-random pattern of ||A||, ||K||, and ||R|| codes and

retransmitted, if not, the Inter Packet Gap (IPG) will be

retransmitted as the same XAUI codes as in the first full

IDLE column.

For most applications, the XAUI_EN bit high configuration is

the most desirable, and is the default.

Table 1. VALID 10b/8b DECODER & ENCODER PATTERNS

RECEIVING SERDES

INTERNAL DATA

TRANSMITTING SERDES

NOTES

SERIAL CODE,

CHARACTER

TRANS_EN

BIT(4)

E-BIT

K-BIT

INTERNAL

FIFO DATA

AKR_SM_

EN(4)

SERIAL

CHARACTER

SERIAL

CODE

DESCRIPTION

Valid Data

0-FF’h

See 802.3

Table

Valid Data

Same Data Value as Received

/K/ (Sync) K28.5

07’h (2)

/A/ /K/ /R/

IEEE802.3ae algorithm

BC (1)

/K/

K28.5

Comma (Sync)

/A/ (Align) K28.3

07’h (2)

/A/ /K/ /R/

IEEE802.3ae algorithm

7C (1)

/A/

K28.3

Align

/R/ (Skip) K28.0

07’h (2)

/A/ /K/ /R/

IEEE802.3ae algorithm

1C (1)

/R/

K28.0

Alternate Idle (Skip)

/S/ K27.7

/S/

K27.7

Start

/T/ K29.7

/T/

K29.7

Terminate

K28.1

Extra comma

/F/ K28.2

/F/

K28.2

Signal Ordered_Set

/Q/ K28.4

/Q/

K28.4

Sequence Ordered_Set

K28.6

K28.7

Repeat has False Comma

K23.7

/E/ K30.7

/E/

K30.7

Error Code

Any other

= ERROR reg.(3)

Invalid code

Error Code

Note (1): First incoming IDLE only, subsequent IDLEs in that block repeat first received code.

Note (2): Default value, actually set by ‘Internal Idle’ register, [3:4].C003’h, see Table 67 and Table 83.

Note (3): Value set by ‘ERROR Code’ register, [3:4].C002’h, see Table 66 and Table 66. The XAUI_EN bit forces it to 1FE’h.

Note (4): If the XAUI_EN bit is set, the ISL35822 acts as though both the TRANS_EN and AKR_EN bits are set.

ISL35822

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